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How do hypervisors handle second-level address translation?

Technologies, such as SLAT, can help improve VM performance by handling address translation through the processor.

Virtualization has changed the way server resources are distributed and used in enterprise workloads. The days...

when a server hosted a single physical application are long gone, and virtual machines can utilize almost all of a server's computing resources. Server administrators must ensure that each virtual machine receives adequate processor, memory, storage and network resources. But workload performance and stability are often most affected by memory, and memory shortages or performance issues can have a profound impact on VMs -- even the entire server.

Modern computers treat memory as a "virtual" resource even when hypervisors are not used. When a program tries to access memory, the computer must translate the virtual address to a physical address. This is handled through a page table or translation lookaside buffer.

Virtualization complicates this process. When a hypervisor adds a virtualization layer to the computer, this translation has to be performed twice; first to translate the VM's virtualized address to the host computer's virtual address scheme, and second to translate the host computer's virtual address scheme to its physical, or machine, address.

This second-level address translation (SLAT) was normally handled in virtual machine manager software -- part of the hypervisor, such as VMware's ESXi -- but the need for additional memory address translation cycles could slow VM performance anytime address translation is needed. Processor manufacturers like Intel and AMD realized that VM performance could be improved by handling second-level address translation directly through the processor.

Intel's implementation of second-level address translation is called extended page tables and is implemented in Westmere-EX core Xeon processors for servers -- with some desktop and mobile versions also. These include products in Intel's E7-88xx, E7-48xx and E7-28xx families as well as E56xx, L56xx and X56xx products. AMD implements SLAT through rapid virtualization indexing  which is also dubbed nested page tables. Rapid virtualization indexing appeared in Barcelona core Opteron processors.

Remember that some hypervisors, such as Hyper-V in Windows 8, abandon software-based memory virtualization and require hardware-assisted second-level address translation for normal operation. Be sure to check for system requirements before deploying or upgrading hypervisors to ensure the new hypervisor will function properly on a non- second-level address translation hardware platform. If not, a hardware upgrade will be required to provide a SLAT-capable processor.

Next Steps

Monitoring VMware memory and CPU use

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Hypervisor memory paging techniques and capabilities

This was last published in March 2016

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