AMD introduced a second version of its I/O virtualization technology specification today. This latest specification...
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extends AMD's I/O Memory Management Unit (IOMMU) benefits to provide secure, scalable, high-performance for I/O virtualization in x86-based servers and computers.
AMD Virtualization Technology (AMD-V) and the AMD I/O Virtualization Technology (IOMMU) Specification revision 1.20 are also designed to provide high throughput and overall system efficiency.
The new specifications are a big step in the right direction, according to analysts. "There's no single magic bullet to banishing I/O inefficencies as evidenced by the multiple technologies embodied by IOMMU," said Illuminata analyst Gordon Haff. "And that's what it will take; concerted chipping away by all the players in the ecosystem."
Burton Group analyst Chris Wolf gives the revisions a stronger endorsement, advising IT managers procuring virtualization to get this spec because it allows for significant performance gains, and security. "Aside from the security, the new hardware assisted memory virtualization will offer substantial performance gains," Wolf said. "The architecture gives virtual machines direct access to I/O. The trade off is you lose some of the hardware independence."
AMD first made its I/O virtualization technology specification widely available in February 2006 through royalty-free licenses to encourage its adoption by hardware and software developers.
"In the time since it first came out, we've received customer and partner feedback and have done some work with partners to improve it, especially in terms of reliability and security," said Margaret Lewis, director of software solutions at AMD. "We have taken the spec to another level of security and reliability, making sure we conform to evolving standards in the relatively new virtualization space."
With quad-core processors now being used to run applications, IOMMU provides the platform for virtual machines to manage I/O devices in a secure and efficient manner, according to Terri Hall, vice president Business Development, Strategic Alliances at AMD.
IOMMU revision 1.20 offers the following enhancements to handle the needs of a wide range of systems:
- Enhanced security and system reliability adds precise device access control to protect against malicious or errant device DMA.
- Enhanced virtualization capabilities improves performance and scalability by enabling direct device access by applications reducing overhead in guest and device paths.
- Open Standards designed to conform to PCI-Sig IOV and ATS standards
- Interrupt remapping enables central management of interrupts in a virtualized system.
- ACPI tables provide information from platform firmware to system software of key I/O topology information
- Enhanced error recovery provides information for efficient detection and recovery from page faults and errors.
The specification is designed to be used by hypervisors and operating systems in both virtualized and non-virtualized environments, and is useful for server consolidation, protecting operating system integrity, and secure initialization, AMD reports.
Looking at these features, Wolf said: "Reliability comes with the ability to isolate channels. This hardware allows isolation in the entire I/O channel, allowing you to prevent errors and security vulnerability on one virtual machine from affecting other virtual machines."
Generally, said Wolf, support for nested paging in AMD's Opteron processor is a big plus for virtualized envionrments. "It allows virtual machines to have access to physical memory, instead of just shadow paging," he noted. "This really helps with performance when there are hundreds and even thousands of (concurrent client connections) by giving access to hardware. Not having access to physical memory slows the machines. This is what has kept companies running enterprise applications from virtualizing."
The I/O specification is one aspect of AMD's Torrenza initiative. "Torrenza" represents an open, customer-centric x86 platform, with AMD64 architecture that enables other processor and hardware providers to innovate within a common ecosystem.
This latest version is the basis for AMD's Tightly Coupled Accelerators, allowing third-party chipsets to perform specific functions while off-loading general computing functions managed by the AMD Opteron processor.
Let us know what you think about the story; e-mail: Bridget Botelho, News Writer.