The Nested Page Table (NPT) technology in Advanced Micro Devices Inc.'s quad-core processor Barcelona may be the answer to virtualizing large workloads, said a prominent VMware Inc. engineer.
Rapid Virtualization Indexing (RVI), a feature of AMD's third-generation Opteron, includes NPT, which help reduce the performance overhead of virtualizing large applications such as databases.
Richard McDougall, a principal engineer and the chief performance architect in the Office of the CTO at VMware Inc., gave a session at the June Usenix conference in Boston in which he gave the technology high praise.
"With AMD NPT, we have come to a turning point. It looks like exactly the right answer going forward … and there is less memory overhead -- less than 5%," McDougall told session attendees.
According to AMD's director of commercial solutions and software strategy, Margaret Lewis, "Large applications that users don't want to virtualize because of the possible performance overhead will benefit from RVI. It is the next step in hardware-assisted virtualization."How NPT works
OSes use processor paging to isolate these processes' addresses and use memory. Paging is the process of translating a process-specific address to a system's physical address.
But when virtualization is thrown into the mix, address translation becomes a challenge because virtual machines (VMs) don't have native direct access to the host server memory, according to an AMD white paper on NPT. As a result, a hypervisor ends up virtualizing a "read only" layer of memory between physical memory and the page tables in the guest OS, which is known as shadow paging.
Unfortunately, creating shadow pages requires CPU and memory, and this adds extra performance overhead, said Tim Mueting, AMD's manager of virtualization solutions.
"With shadow paging, the guest OS and the hypervisor have duplicates, so double the work is being done," Mueting said.
To solve this problem, AMD introduced hardware support for a second or nested level of address translation, now used in Barcelona processors with RVI.
With nested paging, a page table in the hardware takes care of the translation between the guest address of a VM and the physical address, reducing overhead, Mueting said.
Intel Corp. has announced a similar technology that it calls Extended Page Tables (EPT) , which will be available in its next-generation eight-core microarchitecture, code-named "Nehalem," slated for production later this year.NPT: The bigger the workload, the better
With nested paging, the benefits of AMD-V technology becomes more apparent as workload size increases, Mueting said.
"Because of the nature of Nested Page Tables, we see better results with larger workloads when looking at virtualization without NPT," he said. "If I am running Xen or VMware workloads against a database server, I will see an improvement, because it requires lots of memory and a lot of translating goes on. We have also seen performance increases in Web servers. We also see improvements across the board with 64-bit applications."
Still, if a user consolidates a small handful of 32-bit file servers with VMware and running them on AMD Barcelona with virtualization-assist technology, he won't see a huge performance increase, because the workload is relatively small, Lewis said.
" File servers don't offer the type of workload that [nested paging] can really improve on. But if you give it a large database environment, NPT in RVI really becomes a benefit," Lewis said.
AMD-V technology with NPT works with all VMware software since the 3.5.1 release and all versions of Xen since Xen 3.2. It does not work with Microsoft's current version of Hyper-V, but Mueting expects that future releases will.